iconSpEx Engine for Analog IP Reuse

pareto

Not far from digital design, imagine you could update your analog design for different requirements of speed, power and area without compromising functionality with the same ease and readiness: DFchip has already made it real. With SpEx (Specification Explorer), a single IP can generate a group of similar IPs with the same features but different performances, enabling easy analog IP reuse.

PVT ready within hours

Maintaining all other specifications, SpEx optimizes one target performance while sweeping another. At the end, a number of circuits ready for use and verified throughout PVT corners are available. On top of that, the IP generation is achieved in a few hours!

Ready for use

DFchip is working for a better design ecosystem where mixed-signal systems may be conceived more effectively and faster. For more details, please check the following example.

Example: Miller Compensated OpAmp

It is known that power consumption and bandwidth present an important trade-off in amplifiers. We applied the methodology to a simple miller-compensated OpAmp designed in standard TSMC 180nm and we were able to generate 8 amplifiers with different gain-bandwidth products and minimized power consumption within 6 hours. For each point of the curve, all other specifications, such as gain, phase margin, slew rate and PSRR, were maintained. The results are presented below.

miller amplifier
miller amplifier
  • 8 amplifiers
  • 4 other specifications satisfied
  • Open loop gain
  • Phase margin
  • Slew rate
  • PSRR
  • PVT variations taken into account
  • Trade-off information
  • 45 minutes per circuit on ordinary PC
  • Any other trade-off can be studied

Tested in technology nodes from 150nm to 0.6μm in several foundries

You can find the documentation of some of these IPs below.

Designed Circuit

Wideband OpAmp

Low Power LDO

Bandgap Voltage Reference

Programable Gain Amplifier

Foundry / Technology

Silterra 180nm

XFAB 0.6um

XFAB 0.6um

XFAB 180nm

Analysed Trade-off

Settling time x Precision

Load current x Area estimate

Settling time x Supply current

Bandwidth x Supply current

Coming Soon

DFchip is working to include local variations into consideration in the automatic solution to guarantee a high yield for all circuits. At this moment, once a specific set of specifications is chosen by a customer, then, local variation are manually taken into account.

A circuit fulfilling PVT corners is a good starting point and enables us to gain productivity in comparison with a new design.

For more information or to have your IPs multiplied, please contact us at info@dfchip.com

ComingSoon